1. Field of the Invention
The present invention is related to a storage device; particularly, to a multi-channel hybrid density memory storage device and control method thereof.
2. Description of Related Art
It is very time-consuming to read/write date from/into storage device. For accelerating access speed of the storage device, prior arts mostly place a plurality of memories in the storage device, and connect these memories in parallel, simultaneously storing and accessing data in many memories, thereby increase data access speed.
Please refer to FIG. 1, a schematic diagram of a prior art multi-channel memory storage device is shown, wherein two groups of memories connected in parallel are taken as an example for illustrating the operations of data access in a dual-channel memory storage device. As shown in FIG. 1, a multi-channel memory storage device 13 is applied in a digital system 1, and the storage device 13 is coupled to a host 11 to accept instructions from the host 11, performing data read or write.
The multi-channel memory storage device 13 comprises a control unit 131 and six memories A˜F. The control unit 131, coupled between the host 11 and the six memories A˜F, for receiving one of the instructions from the host 11, so as to access the data in a logical block address to which the instruction corresponds into the memories A˜F. The memories A˜F is further divided into two groups, in which memories A, B, C are in the same group, while memories D, E, F are in the other group. The memories A, B, C and memories D, E, F are coupled to the control unit 131 respectively through data transmission lines 135, 139 and instruction transmission lines 133, 137 to transmit data and instructions. By using two instruction transmission lines 133, 137 to transfer different instructions, it is possible to allow the above-mentioned two groups of memories to perform differing access actions at the same time.
Next, please refer to FIG. 2, another schematic diagram of a prior art multi-channel memory storage device is shown, which is a variation from the one depicted in FIG. 1. As illustrated in FIG. 2, compared with FIG. 1, memories A, B, C and memories D, E, F are coupled to the control unit 131 respectively through data transmission lines 235, 237 and a common instruction transmission line 233 to transfer data and instructions. Herein by using one common instruction transmission line 233 to send instructions, it is possible to allow the above-mentioned two groups of memories to simultaneously reading or writing.
Usually, the memories employed in storage devices are either completely Multi-level-cell (MLC) or completely Single-level-cell (SLC), wherein the memories composed of MLC are referred as High Density Memory (HDM), and the memories composed of SLC are known as Low Density Memory (LDM). The LDM provides advantages of fast data access speed, high reliability, greater number of endurance; while HDM offer features of greater storage capacity and low cost. Hence, in view of the characteristics of both two types of memory, there is another type of memory having these two types of memory installed together in one single storage device, referred to as Hybrid Density Memory.
While the architecture of multi-channel memory storage device has become mature, however, the architecture and method for applying Hybrid Density Memory onto multi-channel concept have not yet been proposed so far, as a result, it is an issue desirable to be addressed about how to allocate HDM and LDM under the multi-channel system architecture, in order to exploit the advantages of both types of memory for efficient data access.